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fix tests, add subroutines and slices to SPEC

This commit is contained in:
zongor 2026-07-10 22:54:45 -07:00
parent 470ff4ab20
commit 54eaea2424
9 changed files with 207 additions and 357 deletions
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19
docs/SPECIFICATION.org
View File

@ -223,6 +223,17 @@ Array of a specific plex
«plex»[«length»] «variable» = [val1, val2, ...];
#+end_src ul
*** Slice
:PROPERTIES:
:CUSTOM_ID: slice
:END:
A slice of a array
#+begin_src ul
«plex»[] «variable» = array[start:end];
#+end_src ul
** Plexs
:PROPERTIES:
:CUSTOM_ID: plexs
@ -336,6 +347,14 @@ function «token» («parameter» «plex», ...) «return_plex» {
- calc functions
- statistical functions
** Subroutines
:PROPERTIES:
:CUSTOM_ID: subroutines
:END:
Subroutines are similar to functions but have a few special properties.
They do not use the stack at all, this makes subroutines faster but they will loose any values allocated immediatly after exiting the subroutine.
Use them similar to pure functions.
** Localization
:PROPERTIES:
:CUSTOM_ID: localization

1
test/attack.ul
View File

@ -18,5 +18,4 @@ function print(str string) {
write = string[i];
i = i + 1;
}
write = '\n';
}

7
test/bf.ul
View File

@ -1,20 +1,21 @@
//plex Console
//{
// ref function vector(void):void;
// ref vector;
// byte read;
// u32 pad;
// byte type;
// byte write;
// byte error;
// u16 pad2;
// ref byte[] addr;
// ref addr;
// byte mode;
// byte exec;
//}
//
//Console console = devmap(0x10, Console);
str code = "++++++++[>++++[>++>+++>+++>+<<<<-]>+>+>->>+[<]<-]>>.>---.+++++++..+++.>>.<-.<.+++.------.--------.>>+.>++.";
str code = "+++++++++++[>++++++>+++++++++>++++++++>++++>+++>+<<<<<<-]>+++
+++.>++.+++++++..+++.>>.>-.<<-.<.+++.------.--------.>>>+.>-.";
byte[10000] memory;
nat mp = 0; // memory pointer

6
test/paint.ul
View File

@ -9,7 +9,7 @@ const byte GRAY = 146;
byte selected_color = 255;
plex System {
ref function vector(void):void;
ref vector;
byte wst;
byte rst;
u32 pad;
@ -21,7 +21,7 @@ plex System {
}
plex Screen {
ref function vector(void):void;
ref vector;
nat width;
nat height;
nat auto;
@ -33,7 +33,7 @@ plex Screen {
}
plex Mouse {
ref function vector(void):void;
ref vector;
nat x;
nat y;
nat state;

57
test/tal/attack.tal
View File

@ -1,13 +1,13 @@
|100
LIT2r 0000
!{ @msg $2 } ;{ #0002 ADD2 } !{ 20 64 61 6d 61 67 65 20 69 6e 66 6c 69 63 74 65 64 21 5c 6e 00 } ;msg STA2
!{ @AT $2 } #000e ;AT STA2
!{ @accuracy $2 } #0096 ;accuracy STA2
!{ @dmg $2 } ;AT LDA2 ;accuracy LDA2 calc_damage_ ;dmg STA2
;dmg LDA2 nat_to_str_ str/<print>
;msg LDA2 str/<print>
POP2r BRK @calc_damage_ ( at accuracy -- res )
;dmg LDA2 nat_to_str_ print_
;msg print_
POP2r BRK
@calc_damage_ ( at accuracy -- res )
OVR2r LIT2r 0004 SUB2r
STH2kr STA2
STH2kr #0002 ADD2 STA2
@ -15,6 +15,21 @@ POP2r BRK @calc_damage_ ( at accuracy -- res )
STH2kr LDA2 STH2kr #0002 ADD2 LDA2 MUL2 #0014 DIV2 #0003 SUB2 !&return &return
POP2r JMP2r
@print_ ( string -- )
OVR2r LIT2r 0004 SUB2r
STH2kr STA2
STH2kr #0002 ADD2 LDA2
#0000 STH2kr #0002 ADD2 STA2
&while.0 STH2kr #0002 ADD2 LDA2 STH2kr LDA2 LDA2 LTH2 #03 JCN !{
STH2kr LDA2 #0002 ADD2 STH2kr #0002 ADD2 LDA2 ADD2 LDA #18 DEO
STH2kr #0002 ADD2 LDA2 #0001 ADD2 STH2kr #0002 ADD2 STA2
!&while.0 }
#0a #18 DEO
&return
POP2r JMP2r
@sext
#80 ANDk EQU #ff MUL SWP JMP2r
@ -28,17 +43,29 @@ POP2r BRK @calc_damage_ ( at accuracy -- res )
&return
POP2r JMP2r
@afree_ ( -- result* )
OVR2r #0000 ;mem_length_ STA2
#0000
&return
POP2r JMP2r
@amcpy_ ( length* from* -- result* )
OVR2r LIT2r 0008 SUB2r STH2kr #0006 ADD2 STA2
STH2kr #0004 ADD2 STA2
OVR2r LIT2r 000a SUB2r STH2kr #0008 ADD2 STA2
STH2kr #0006 ADD2 STA2
STH2kr #0006 ADD2 LDA2 INC2 INC2 STH2kr #0004 ADD2 STA2
STH2kr #0004 ADD2 LDA2 aalloc_
STH2kr INC2 INC2 STA2
#0000 STH2kr STA2
STH2kr #0006 ADD2 LDA2 #00ff AND2 NIP sext
STH2kr INC2 INC2 LDA2 STA
POP STH2kr #0006 ADD2 LDA2 #08 SFT2 #00ff AND2 NIP sext
STH2kr INC2 INC2 LDA2 INC2 STA
POP #0000 STH2kr STA2
&begin.1
STH2kr LDA2 STH2kr #0004 ADD2 LDA2 LTH2 #00 EQU ?&break.1
STH2kr #0006 ADD2 LDA2 STH2kr LDA2 ADD2 LDA sext
STH2kr INC2 INC2 LDA2 STH2kr LDA2 ADD2 STA
STH2kr LDA2 STH2kr #0006 ADD2 LDA2 LTH2 #00 EQU ?&break.1
STH2kr #0008 ADD2 LDA2 STH2kr LDA2 ADD2 LDA sext
STH2kr INC2 INC2 LDA2 STH2kr LDA2 INC2 INC2 ADD2 STA
POP
&continue.1
@ -71,11 +98,5 @@ POP2r BRK @calc_damage_ ( at accuracy -- res )
&return
POP2r JMP2r
@str/<print> ( str* -- )
LDAk DUP ?{ POP POP2 JMP2r }
#18 DEO
INC2 !/<print>
@mem_length_ #0000
@mem_
@mem_length_ #0015
@mem_ @msg 0014 20 64 61 6d 61 67 65 20 69 6e 66 6c 69 63 74 65 64 21 0a 00

69
test/tal/bang.tal
View File

@ -1,69 +0,0 @@
|100
!{ @flag $1 } #0000 ;flag STA2
;flag LDA2 #0000 EQU2 #03 JCN !{ ;{ #0002 ADD2 } !{ 66 6c 61 67 20 69 73 20 66 61 6c 73 65 00 } str/<print>
!&if_end.0 } &if_end.0 BRK
@sext
#80 ANDk EQU #ff MUL SWP JMP2r
@aalloc_ ( size* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
;mem_length_ LDA2 STH2kr STA2
;mem_length_ LDA2k STH2kr INC2 INC2 LDA2 ADD2 SWP2 STA2
;mem_ STH2kr LDA2 ADD2 !&return
#0000
&return
POP2r JMP2r
@amcpy_ ( length* from* -- result* )
OVR2r LIT2r 0008 SUB2r STH2kr #0006 ADD2 STA2
STH2kr #0004 ADD2 STA2
STH2kr #0004 ADD2 LDA2 aalloc_
STH2kr INC2 INC2 STA2
#0000 STH2kr STA2
&begin.1
STH2kr LDA2 STH2kr #0004 ADD2 LDA2 LTH2 #00 EQU ?&break.1
STH2kr #0006 ADD2 LDA2 STH2kr LDA2 ADD2 LDA sext
STH2kr INC2 INC2 LDA2 STH2kr LDA2 ADD2 STA
POP
&continue.1
STH2kr LDA2k INC2k ROT2 STA2
POP2 !&begin.1
&break.1
STH2kr INC2 INC2 LDA2 !&return
#0000
&return
POP2r JMP2r
@nat_to_str_ ( n* -- result* )
OVR2r LIT2r 000a SUB2r STH2kr #0008 ADD2 STA2
#0005 STH2kr STA2
&begin.1
STH2kr #0008 ADD2 LDA2 #000a OVR2 OVR2 DIV2 MUL2 SUB2 #0030 ADD2 STH2kr INC2 INC2 STH2kr LDA2k #0001 SUB2 SWP2 STA2k
POP2 ADD2 STA
POP STH2kr #0008 ADD2 LDA2k #000a DIV2 SWP2 STA2
&continue.1
#0000 STH2kr #0008 ADD2 LDA2 LTH2 ?&begin.1
&break.1
#0005 STH2kr LDA2 SUB2 STH2kr INC2 INC2 STH2kr LDA2 ADD2 amcpy_
!&return
#0000
&return
POP2r JMP2r
@str/<print> ( str* -- )
LDAk DUP ?{ POP POP2 JMP2r }
#18 DEO
INC2 !/<print>
@mem_length_ #0000
@mem_

310
test/tal/bf.tal
View File

@ -1,69 +1,51 @@
|100
LIT2r 0000
!{ @code $2 } ;{ #0002 ADD2 } !{ 2b 2b 2b 2b 2b 2b 2b 2b 5b 3e 2b 2b 2b 2b 5b 3e 2b 2b 3e 2b 2b 2b 3e 2b 2b 2b 3e 2b 3c 3c 3c 3c 2d 5d 3e 2b 3e 2b 3e 2d 3e 3e 2b 5b 3c 5d 3c 2d 5d 3e 3e 2e 3e 2d 2d 2d 2e 2b 2b 2b 2b 2b 2b 2b 2e 2e 2b 2b 2b 2e 3e 3e 2e 3c 2d 2e 3c 2e 2b 2b 2b 2e 2d 2d 2d 2d 2d 2d 2e 2d 2d 2d 2d 2d 2d 2d 2d 2e 3e 3e 2b 2e 3e 2b 2b 2e 00 } ;code STA2
;code LDA2 bf_ POP2r BRK @bf_ ( code -- )
OVR2r LIT2r 000a SUB2r
STH2kr STA2
STH2kr #2712 ADD2 LDA2
STH2kr #2714 ADD2 LDA2
#0000 STH2kr #2714 ADD2 STA2
&while.0 STH2kr #2714 ADD2 LDA2 #006a LTH2 #03 JCN !{
STH2kr #0004 ADD2 LDA2 #0000 LTH2 #03 JCN !{
!&if_end.0 } &if_end.0
STH2kr #0004 ADD2 LDA2 #006a GTH2 !&return STH2kr #0002 ADD2 LDA2 ;memory LDA2 GTH2 #03 JCN !{
!&return !&if_end.1 } &if_end.1
STH2kr LDA2 #03 JCN !{
!&if_end.2 } &if_end.2
STH2kr #0004 ADD2 LDA2 #0027 STH2kr #0002 ADD2 LDA2 #0001 ADD2 STH2kr #0002 ADD2 STA2 STH2kr LDA2 #03 JCN !{
!&if_end.3 } &if_end.3
STH2kr #0004 ADD2 LDA2 #0027 STH2kr #0002 ADD2 LDA2 #0001 SUB2 STH2kr #0002 ADD2 STA2 STH2kr LDA2 #03 JCN !{
!&if_end.4 } &if_end.4
STH2kr #0004 ADD2 LDA2 #0027 ;memory STH2kr #0002 ADD2 LDA2 #0001 MUL2 ADD2 #0002 ADD2 LDA2 ;memory STH2kr #0002 ADD2 LDA2 #0001 MUL2 ADD2 #0002 ADD2 LDA2 #0001 ADD2 STH2kr LDA2 #03 JCN !{
!&if_end.5 } &if_end.5
STH2kr #0004 ADD2 LDA2 #0027 ;memory STH2kr #0002 ADD2 LDA2 #0001 MUL2 ADD2 #0002 ADD2 LDA2 ;memory STH2kr #0002 ADD2 LDA2 #0001 MUL2 ADD2 #0002 ADD2 LDA2 #0001 SUB2 STH2kr LDA2 #03 JCN !{
!&if_end.6 } &if_end.6
STH2kr #0004 ADD2 LDA2 #0027 ;memory STH2kr #0002 ADD2 LDA2 #0001 MUL2 ADD2 #0002 ADD2 LDA2 #18 DEO STH2kr LDA2 #03 JCN !{
!&if_end.7 } &if_end.7
STH2kr #0004 ADD2 LDA2 #0027 ;memory STH2kr #0002 ADD2 LDA2 #0001 MUL2 ADD2 #0002 ADD2 LDA2 #12 DEI STH2kr LDA2 #03 JCN !{
!&if_end.8 } &if_end.8
STH2kr #0004 ADD2 LDA2 #0027 ;memory STH2kr #0002 ADD2 LDA2 #0001 MUL2 ADD2 #0002 ADD2 LDA2 #0000 EQU2 #03 JCN !{
!{ @mp $2 } #0000 ;mp STA2
!{ @ip $2 } #0000 ;ip STA2
&while.0 ;ip LDA2 ;code LDA2 LTH2 #03 JCN !{
;code #0002 ADD2 ;ip LDA2 ADD2 LDA #3e EQU #03 JCN !{
;mp LDA2 #0001 ADD2 ;mp STA2
!&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #3c EQU #03 JCN !{
;mp LDA2 #0001 SUB2 ;mp STA2
!&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #2b EQU #03 JCN !{
;memory ;mp LDA2 #0002 MUL2 ADD2 #0002 ADD2 ;memory ;mp LDA2 #0002 MUL2 ADD2 #0002 ADD2 LDA #01 ADD ROT ROT STA
!&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #2d EQU #03 JCN !{
;memory ;mp LDA2 #0002 MUL2 ADD2 #0002 ADD2 ;memory ;mp LDA2 #0002 MUL2 ADD2 #0002 ADD2 LDA #01 SUB ROT ROT STA
!&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #2e EQU #03 JCN !{
;memory ;mp LDA2 #0002 MUL2 ADD2 #0002 ADD2 LDA #18 DEO
!&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #2c EQU #03 JCN !{
;memory ;mp LDA2 #0002 MUL2 ADD2 #0002 ADD2 #12 DEI ROT ROT STA
!&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #5b EQU #03 JCN !{
;memory ;mp LDA2 #0002 MUL2 ADD2 #0002 ADD2 LDA #0000 EQU2 #03 JCN !{
STH2kr LDA2
#0001 STH2kr STA2
&while.1 STH2kr LDA2 #0000 GTH2 #03 JCN !{
STH2kr #0004 ADD2 LDA2 #0001 ADD2 STH2kr #0004 ADD2 STA2 STH2kr LDA2 #03 JCN !{
!&if_end.9 } &if_end.9
STH2kr #0004 ADD2 LDA2 #0027 STH2kr LDA2 #0001 ADD2 STH2kr STA2 STH2kr LDA2 #03 JCN !{
!&if_end.10 } &if_end.10
STH2kr #0004 ADD2 LDA2 #0027 STH2kr LDA2 #0001 SUB2 STH2kr STA2 !&while.1 }
!&if_end.11 } &if_end.11
STH2kr LDA2 #03 JCN !{
!&if_end.12 } &if_end.12
STH2kr #0004 ADD2 LDA2 #0027 ;memory STH2kr #0002 ADD2 LDA2 #0001 MUL2 ADD2 #0002 ADD2 LDA2 #03 JCN !{
;ip LDA2 #0001 ADD2 ;ip STA2
;code #0002 ADD2 ;ip LDA2 ADD2 LDA #5b EQU #03 JCN !{
STH2kr LDA2 #0001 ADD2 STH2kr STA2
!&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #5d EQU #03 JCN !{
STH2kr LDA2 #0001 SUB2 STH2kr STA2
!&if_end.0 } !&while.1 }
!&if_end.0 } !&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #5d EQU #03 JCN !{
;memory ;mp LDA2 #0002 MUL2 ADD2 #0002 ADD2 LDA #03 JCN !{
STH2kr LDA2
#0001 STH2kr STA2
&while.2 STH2kr LDA2 #0000 GTH2 #03 JCN !{
STH2kr #0004 ADD2 LDA2 #0001 SUB2 STH2kr #0004 ADD2 STA2 STH2kr LDA2 #03 JCN !{
!&if_end.13 } &if_end.13
STH2kr #0004 ADD2 LDA2 #0027 STH2kr LDA2 #0001 ADD2 STH2kr STA2 STH2kr LDA2 #03 JCN !{
!&if_end.14 } &if_end.14
STH2kr #0004 ADD2 LDA2 #0027 STH2kr LDA2 #0001 SUB2 STH2kr STA2 !&while.2 }
!&if_end.15 } &if_end.15
STH2kr #0004 ADD2 LDA2 #0001 ADD2 STH2kr #0004 ADD2 STA2 !&while.0 }
&return
POP2r JMP2r
;ip LDA2 #0001 SUB2 ;ip STA2
;code #0002 ADD2 ;ip LDA2 ADD2 LDA #5d EQU #03 JCN !{
STH2kr LDA2 #0001 ADD2 STH2kr STA2
!&if_end.0 } ;code #0002 ADD2 ;ip LDA2 ADD2 LDA #5b EQU #03 JCN !{
STH2kr LDA2 #0001 SUB2 STH2kr STA2
!&if_end.0 } !&while.2 }
!&if_end.0 } !&if_end.0 } &if_end.0
;ip LDA2 #0001 ADD2 ;ip STA2
!&while.0 }
POP2r BRK
@sext
#80 ANDk EQU #ff MUL SWP JMP2r
@sdiv
OVR #80 AND ?&b_neg &b_pos OVR2 POP #80 AND ?&a_neg_b_pos DIV2 JMP2r &a_neg_b_pos SWP2 #0000 SWP2 SUB2 SWP2 DIV2 #0000 SWP2 SUB2 JMP2r
&b_neg #0000 SWP2 SUB2 OVR2 POP #80 AND ?&a_neg_b_neg DIV2 #0000 SWP2 SUB2 JMP2r
&a_neg_b_neg #0000 ROT2 SUB2 SWP2 DIV2 JMP2r
@aalloc_ ( size* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
@ -75,36 +57,6 @@
&return
POP2r JMP2r
@areturn_ ( size* src* checkpoint* -- result* )
OVR2r LIT2r 000a SUB2r STH2kr #0008 ADD2 STA2
STH2kr #0006 ADD2 STA2
STH2kr #0004 ADD2 STA2
;mem_ STH2kr #0008 ADD2 LDA2 ADD2 STH2kr INC2 INC2 STA2
STH2kr #0006 ADD2 LDA2 STH2kr INC2 INC2 LDA2 NEQ2 ?&end.1
STH2kr #0006 ADD2 LDA2 !&return
&end.1
#0000 STH2kr STA2
&begin.2
STH2kr LDA2 STH2kr #0004 ADD2 LDA2 LTH2 #00 EQU ?&break.2
STH2kr #0006 ADD2 LDA2 STH2kr LDA2 ADD2 LDA sext
STH2kr INC2 INC2 LDA2 STH2kr LDA2 ADD2 STA
POP
&continue.2
STH2kr LDA2k INC2k ROT2 STA2
POP2 !&begin.2
&break.2
STH2kr #0008 ADD2 LDA2 STH2kr #0004 ADD2 LDA2 ADD2 ;mem_length_ STA2
#0000 ;mem_ ;mem_length_ LDA2 ADD2 STA
POP STH2kr INC2 INC2 LDA2 !&return
#0000
&return
POP2r JMP2r
@afree_ ( -- result* )
OVR2r #0000 ;mem_length_ STA2
#0000
@ -113,16 +65,21 @@
POP2r JMP2r
@amcpy_ ( length* from* -- result* )
OVR2r LIT2r 0008 SUB2r STH2kr #0006 ADD2 STA2
STH2kr #0004 ADD2 STA2
OVR2r LIT2r 000a SUB2r STH2kr #0008 ADD2 STA2
STH2kr #0006 ADD2 STA2
STH2kr #0006 ADD2 LDA2 INC2 INC2 STH2kr #0004 ADD2 STA2
STH2kr #0004 ADD2 LDA2 aalloc_
STH2kr INC2 INC2 STA2
#0000 STH2kr STA2
STH2kr #0006 ADD2 LDA2 #00ff AND2 NIP sext
STH2kr INC2 INC2 LDA2 STA
POP STH2kr #0006 ADD2 LDA2 #08 SFT2 #00ff AND2 NIP sext
STH2kr INC2 INC2 LDA2 INC2 STA
POP #0000 STH2kr STA2
&begin.1
STH2kr LDA2 STH2kr #0004 ADD2 LDA2 LTH2 #00 EQU ?&break.1
STH2kr #0006 ADD2 LDA2 STH2kr LDA2 ADD2 LDA sext
STH2kr INC2 INC2 LDA2 STH2kr LDA2 ADD2 STA
STH2kr LDA2 STH2kr #0006 ADD2 LDA2 LTH2 #00 EQU ?&break.1
STH2kr #0008 ADD2 LDA2 STH2kr LDA2 ADD2 LDA sext
STH2kr INC2 INC2 LDA2 STH2kr LDA2 INC2 INC2 ADD2 STA
POP
&continue.1
@ -155,176 +112,5 @@
&return
POP2r JMP2r
@int_to_str_ ( n* -- result* )
OVR2r LIT2r 000c SUB2r STH2kr #000a ADD2 STA2
#0006 STH2kr INC2 INC2 STA2
STH2kr #000a ADD2 LDA2 #8000 EOR2 #8000 LTH2 #00 SWP #0000 NEQ2 #00 SWP STH2kr STA
POP LDAkr STHr sext
#0000 EQU2 ?&end.1
#0000 STH2kr #000a ADD2 LDA2 SUB2 STH2kr #000a ADD2 STA2
&end.1
&begin.2
STH2kr #000a ADD2 LDA2 #000a OVR2 OVR2 sdiv/b_pos
MUL2 SUB2 #0030 ADD2 STH2kr #0004 ADD2 STH2kr INC2 INC2 LDA2k #0001 SUB2 SWP2 STA2k
POP2 ADD2 STA
POP STH2kr #000a ADD2 LDA2k #000a sdiv/b_pos
SWP2 STA2
&continue.2
#8000 STH2kr #000a ADD2 LDA2 #8000 EOR2 LTH2 ?&begin.2
&break.2
LDAkr STHr sext
#0000 EQU2 ?&end.3
#002d STH2kr #0004 ADD2 STH2kr INC2 INC2 LDA2k #0001 SUB2 SWP2 STA2k
POP2 ADD2 STA
POP
&end.3
#0006 STH2kr INC2 INC2 LDA2 SUB2 STH2kr #0004 ADD2 STH2kr INC2 INC2 LDA2 ADD2 amcpy_
!&return
#0000
&return
POP2r JMP2r
@int_to_nat_ ( n* -- result* )
OVR2r LIT2r 0002 SUB2r STH2kr STA2
STH2kr LDA2 !&return
#0000
&return
POP2r JMP2r
@nat_to_int_ ( n* -- result* )
OVR2r LIT2r 0002 SUB2r STH2kr STA2
STH2kr LDA2 !&return
#0000
&return
POP2r JMP2r
@int_add_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr INC2 INC2 LDA2 STH2kr LDA2 ADD2 !&return
#0000
&return
POP2r JMP2r
@int_sub_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr INC2 INC2 LDA2 STH2kr LDA2 SUB2 !&return
#0000
&return
POP2r JMP2r
@int_mul_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr INC2 INC2 LDA2 STH2kr LDA2 MUL2 !&return
#0000
&return
POP2r JMP2r
@int_div_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr INC2 INC2 LDA2 STH2kr LDA2 sdiv
!&return
#0000
&return
POP2r JMP2r
@int_eq_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr INC2 INC2 LDA2 STH2kr LDA2 EQU2 #00 SWP !&return
#0000
&return
POP2r JMP2r
@int_ne_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr INC2 INC2 LDA2 STH2kr LDA2 NEQ2 #00 SWP !&return
#0000
&return
POP2r JMP2r
@int_lt_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr INC2 INC2 LDA2 #8000 EOR2 STH2kr LDA2 #8000 EOR2 LTH2 #00 SWP !&return
#0000
&return
POP2r JMP2r
@int_le_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr INC2 INC2 LDA2 #8000 EOR2 STH2kr LDA2 #8000 EOR2 GTH2 #00 SWP #01 EOR !&return
#0000
&return
POP2r JMP2r
@int_gt_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr LDA2 #8000 EOR2 STH2kr INC2 INC2 LDA2 #8000 EOR2 LTH2 #00 SWP !&return
#0000
&return
POP2r JMP2r
@int_ge_ ( b* a* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
STH2kr STA2
STH2kr LDA2 #8000 EOR2 STH2kr INC2 INC2 LDA2 #8000 EOR2 GTH2 #00 SWP #01 EOR !&return
#0000
&return
POP2r JMP2r
@int_neg_ ( f* -- result* )
OVR2r LIT2r 0002 SUB2r STH2kr STA2
#0000 STH2kr LDA2 SUB2 !&return
#0000
&return
POP2r JMP2r
@int_abs_ ( f* -- result* )
OVR2r LIT2r 0002 SUB2r STH2kr STA2
STH2kr LDA2 #8000 EOR2 #8000 LTH2 ?&then.1
STH2kr LDA2 !&end.1
&then.1
#0000 STH2kr LDA2 SUB2
&end.1
!&return
#0000
&return
POP2r JMP2r
@str/<print> ( str* -- )
LDAk DUP ?{ POP POP2 JMP2r }
#18 DEO
INC2 !/<print>
@mem_length_ #0000
@mem_ @memory $10000
@mem_length_ #0080
@mem_ @code 007b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 5b 3e 2b 2b 2b 2b 2b 2b 3e 2b 2b 2b 2b 2b 2b 2b 2b 2b 3e 2b 2b 2b 2b 2b 2b 2b 2b 3e 2b 2b 2b 2b 3e 2b 2b 2b 3e 2b 3c 3c 3c 3c 3c 3c 2d 5d 3e 2b 2b 2b 0a 2b 2b 2b 2e 3e 2b 2b 2e 2b 2b 2b 2b 2b 2b 2b 2e 2e 2b 2b 2b 2e 3e 3e 2e 3e 2d 2e 3c 3c 2d 2e 3c 2e 2b 2b 2b 2e 2d 2d 2d 2d 2d 2d 2e 2d 2d 2d 2d 2d 2d 2d 2d 2e 3e 3e 3e 2b 2e 3e 2d 2e 00 @memory 2710 $10000

93
test/tal/not.tal Normal file
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@ -0,0 +1,93 @@
|100
LIT2r 0000
!{ @flag $1 } #0000 ;flag STA2
;flag LDA2 #0000 EQU2 #03 JCN !{
;{ #0001 ADD2 } !{ 000d 66 6c 61 67 20 69 73 20 66 61 6c 73 65 00 } print_
!&if_end.0 } &if_end.0
POP2r BRK
@print_ ( string -- )
OVR2r LIT2r 0004 SUB2r
STH2kr STA2
STH2kr #0002 ADD2 LDA2
#0000 STH2kr #0002 ADD2 STA2
&while.0 STH2kr #0002 ADD2 LDA2 STH2kr LDA2 LDA2 LTH2 #03 JCN !{
STH2kr LDA2 #0002 ADD2 STH2kr #0002 ADD2 LDA2 ADD2 LDA #18 DEO
STH2kr #0002 ADD2 LDA2 #0001 ADD2 STH2kr #0002 ADD2 STA2
!&while.0 }
#0a #18 DEO
&return
POP2r JMP2r
@sext
#80 ANDk EQU #ff MUL SWP JMP2r
@aalloc_ ( size* -- result* )
OVR2r LIT2r 0004 SUB2r STH2kr INC2 INC2 STA2
;mem_length_ LDA2 STH2kr STA2
;mem_length_ LDA2k STH2kr INC2 INC2 LDA2 ADD2 SWP2 STA2
;mem_ STH2kr LDA2 ADD2 !&return
#0000
&return
POP2r JMP2r
@afree_ ( -- result* )
OVR2r #0000 ;mem_length_ STA2
#0000
&return
POP2r JMP2r
@amcpy_ ( length* from* -- result* )
OVR2r LIT2r 000a SUB2r STH2kr #0008 ADD2 STA2
STH2kr #0006 ADD2 STA2
STH2kr #0006 ADD2 LDA2 INC2 INC2 STH2kr #0004 ADD2 STA2
STH2kr #0004 ADD2 LDA2 aalloc_
STH2kr INC2 INC2 STA2
STH2kr #0006 ADD2 LDA2 #00ff AND2 NIP sext
STH2kr INC2 INC2 LDA2 STA
POP STH2kr #0006 ADD2 LDA2 #08 SFT2 #00ff AND2 NIP sext
STH2kr INC2 INC2 LDA2 INC2 STA
POP #0000 STH2kr STA2
&begin.1
STH2kr LDA2 STH2kr #0006 ADD2 LDA2 LTH2 #00 EQU ?&break.1
STH2kr #0008 ADD2 LDA2 STH2kr LDA2 ADD2 LDA sext
STH2kr INC2 INC2 LDA2 STH2kr LDA2 INC2 INC2 ADD2 STA
POP
&continue.1
STH2kr LDA2k INC2k ROT2 STA2
POP2 !&begin.1
&break.1
STH2kr INC2 INC2 LDA2 !&return
#0000
&return
POP2r JMP2r
@nat_to_str_ ( n* -- result* )
OVR2r LIT2r 000a SUB2r STH2kr #0008 ADD2 STA2
#0005 STH2kr STA2
&begin.1
STH2kr #0008 ADD2 LDA2 #000a OVR2 OVR2 DIV2 MUL2 SUB2 #0030 ADD2 STH2kr INC2 INC2 STH2kr LDA2k #0001 SUB2 SWP2 STA2k
POP2 ADD2 STA
POP STH2kr #0008 ADD2 LDA2k #000a DIV2 SWP2 STA2
&continue.1
#0000 STH2kr #0008 ADD2 LDA2 LTH2 ?&begin.1
&break.1
#0005 STH2kr LDA2 SUB2 STH2kr INC2 INC2 STH2kr LDA2 ADD2 amcpy_
!&return
#0000
&return
POP2r JMP2r
@mem_length_ #0000
@mem_